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december 2000 page 1 cl7128a cl7256a cl7128ae cl7256ae useable gates 2,500 5,000 10,000 macrocells 128 256 512 logic array blocks 8 16 32 max us er i/o pins 100 164 212 speed grades -4, -5, -6, -7, -10, -12 -4, -5, -6, -7, -10, -12 -6, -7, -10, -12 84-pin plcc 100-pin tqfp 144-pin tqfp 100-pin tqfp 100-pin bga 208-pin pqfp 100-pin bga 144-pin tqfp 256-pin bga 144-pin tqfp 208-pin pqfp 256-pin bga 7ka tbl 01a packages feature cl7512a u laser processed logic device (lpld?) technology offers the ultimate combination of performance, flexibility, and low cost u functionally, architecturally, and electrically compatible with industry-standard altera ? max ? 7000 u high density - 2,500 usable gates - 128 macrocells - 100 maximum user i/o pins u laser fuse technology provides very fast, dense interconnect routing u low current consumption u supports 3.3 volt operation u alpha particle immune cl7000 product family overview cl7128a cl7128ae laser processed logic device family
cl7128a and cl7128ae laser processed logic devices page 2 the clear logic cl7000 laser processed logic device (lpld ? ) family offers the ultimate combination of performance, flexibility, and cost. this family is a system level second source to altera max ? 7000a products. for designs not requiring in- system reprogrammability, design verification can be performed using the programmable altera devices, and clear logic lplds can be used for low cost, high volume production. clear logic?s innovative laser-based technology eliminates nre costs, test vector development, ordering minimums and long lead times. no re-simulation or re-layout is required, as the device uses a cell-based, pld-like architecture. clear logic?s nofault ? technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. the clear logic cl7000 laser processed logic device family is based upon a large array of macrocells. each macrocell contains a logic array with five product terms, a product-term select matrix, and a configurable register. a group of sixteen macrocells forms a block. laser-configured metal fuses implement logical functions and control signal routing. laser configuration provides reduced cost and enhanced performance. these inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. for further information on designing with the cl7000 lpld family, please consult the following documents: u an-01: requesting a first article. this document provides instructions on how to submit a bitstream file for generation of first articles. u an-02: clear logic packaging guide. this document provides specifications and drawings for packages used by the cl7000 family. u an-09: cl7000 technology white paper. this document outlines the technologies employed by the cl7000 lpld family. u an-10: calculating cl7000 power consumption. this document provides guidelines for calculating power consumption based on design characteristics. u an-11: cl7000 test methodology. this document discribes how clear logic provides 100% stuck-at fault coverage. description cl7128a and cl7128ae laser processed logic devices additional information
cl7128a and cl7128ae laser processed logic devices page 3 block diagram i n p u t / g c l k 1 i n p u t / o e 2 / g c l k 2 i n p u t / o e 1 i n p u t / g c l r n 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s 3 t o 1 6 i / o p i n s i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k b l o c k a m a c r o c e l l s 1 - 1 6 b l o c k c m a c r o c e l l s 3 3 - 4 8 b l o c k e m a c r o c e l l s 6 5 - 8 0 b l o c k g m a c r o c e l l s 9 7 - 1 1 2 b l o c k b m a c r o c e l l s 1 7 - 3 2 b l o c k d m a c r o c e l l s 4 9 - 6 4 b l o c k f m a c r o c e l l s 8 1 - 9 6 b l o c k h m a c r o c e l l s 1 1 3 - 1 2 8 6 o u t p u t e n a b l e s 6 - 1 0 o u t p u t e n a b l e s 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 l a s e r - c o n f i g u r e d i n t e r c o n n e c t a r r a y ( l i a ) 7 1 2 8 a d r w 0 1 u an-12: cl7000 lpld timing and function compatability. this document shows how a seamless conversion from cpld to asic can be achieve with no additional engineering with clear logic.
cl7128a and cl7128ae laser processed logic devices page 4 macrocell diagram g l o b a l c l o c k s g l o b a l c l e a r l o c a l a r r a y 3 6 s i g n a l s f r o m l i a 1 6 e x p a n d e r p r o d u c t t e r m s s h a r e d l o g i c e x p a n d e r s p r o d u c t t e r m s e l e c t m a t r i x p a r a l l e l l o g i c e x p a n d e r s c l e a r s e l e c t v c c c l o c k / e n a b l e s e l e c t r e g i s t e r b y p a s s f a s t i n p u t s e l e c t c o n f i g u r a b l e r e g i s t e r t o l i a t o i / o c o n t r o l b l o c k f r o m i / o p i n p r n e n a c l r n q d 2 7 k d r w 0 1
cl7128a and cl7128ae laser processed logic devices page 5 pin configuration p i n n a m e 8 4 p i n p l c c 1 0 0 p i n t q f p 1 0 0 p i n f b g a 1 4 4 p i n t q f p 2 5 6 p i n f b g a i n p u t / g c l k 1 8 3 8 7 a 6 1 2 5 d 9 i n p u t / g c l r n 1 8 9 b 5 1 2 7 e 8 i n p u t / o e 1 8 4 8 8 b 6 1 2 6 e 9 i n p u t / o e 2 / g c l k 2 2 9 0 a 5 1 2 8 d 8 t d i 1 4 4 a 1 4 d 4 t m s 2 3 1 5 f 3 2 0 j 6 t c k 6 2 6 2 f 8 8 9 j 1 1 t d o 7 1 7 3 a 1 0 1 0 4 d 1 3 g n d i n t 4 2 , 8 2 3 8 , 8 6 d 6 , g 5 5 2 , 5 7 , 1 2 4 , 1 2 9 a 8 , c 9 , g 9 , k 8 , p 9 g n d 7 , 1 9 , 3 2 , 4 7 , 5 9 , 7 2 1 1 , 2 6 , 4 3 , 5 9 , 7 4 , 9 5 c 3 , d 7 , e 5 , f 6 , g 4 , h 8 3 , 1 3 , 1 7 , 3 3 , 5 9 , 6 4 , 8 5 , 1 0 5 , 1 3 5 a 3 , b 1 0 , c 2 , d 1 4 , f 6 , g 1 0 , h 8 , j 9 , k 7 , l 1 1 , m 3 , p 6 , p 1 0 , r 2 , r 3 , t 1 , t 1 5 v c c i n t 3 , 4 3 3 9 , 9 1 d 5 , g 6 5 1 , 5 8 , 1 2 3 , 1 3 0 b 9 , c 8 , g 8 , k 9 , p 8 v c c i o 1 3 , 2 6 , 3 8 , 5 3 , 6 6 , 7 8 3 , 1 8 , 3 4 , 5 1 , 6 6 , 8 2 c 8 , d 4 , e 6 , f 5 , g 7 , h 3 2 4 , 5 0 , 7 3 , 7 6 , 9 5 , 1 1 5 , 1 4 4 b 3 , b 5 , c 1 4 , e 1 5 , f 1 1 , g 3 , g 7 , g 1 5 , h 9 , j 8 , k 1 0 , l 3 , l 6 , m 1 5 , p 1 4 , t 2 , t 3 n c ( n o c o n n e c t ) - - - 1 , 2 , 1 2 , 1 9 , 3 4 , 3 5 , 3 6 , 4 3 , 4 6 , 4 7 , 4 8 , 4 9 , 6 6 , 7 5 , 9 0 , 1 0 3 , 1 0 8 , 1 2 0 , 1 2 1 , 1 2 2 a 1 , a 2 , a 4 , a 5 , a 6 , a 7 , a 9 , a 1 0 , a 1 1 , a 1 2 , a 1 3 , a 1 4 , a 1 5 , a 1 6 , b 1 , b 2 , b 4 , b 6 , b 7 , b 8 , b 1 1 , b 1 2 , b 1 3 , b 1 4 , b 1 5 , b 1 6 , c 1 , c 3 , c 4 , c 6 , c 1 1 , c 1 3 , c 1 5 , c 1 6 , d 1 , d 2 , d 3 , d 1 5 , d 1 6 , e 1 , e 2 , e 3 , e 1 4 , e 1 6 , f 1 , f 2 , f 1 5 , f 1 6 , g 1 , g 2 , g 1 4 , g 1 6 , h 1 , h 2 , h 1 5 , h 1 6 , j 1 , j 2 , j 1 5 , j 1 6 , k 1 , k 2 , k 3 , k 1 4 , k 1 5 , k 1 6 , l 1 , l 2 , l 1 5 , l 1 6 , m 1 , m 1 4 , m 1 6 , n 1 , n 2 , n 3 , n 1 4 , n 1 5 , n 1 6 , p 1 , p 2 , p 3 , p 4 , p 1 2 , p 1 3 , p 1 5 , p 1 6 , r 1 , r 4 , r 5 , r 6 , r 7 , r 8 , r 9 , r 1 1 , r 1 2 , r 1 3 , r 1 4 , r 1 5 , r 1 6 , t 4 , t 5 , t 6 , t 7 , t 8 , t 9 , t 1 0 , t 1 1 , t 1 2 , t 1 3 , t 1 4 , t 1 6 t o t a l u s e r i / o p i n s 6 8 8 4 8 4 1 0 0 1 0 0 7 1 2 8 a t b l 0 1
cl7128a and cl7128ae laser processed logic devices page 6 absolute maximum ratings dc electrical s pecifications s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t v c c s u p p l y v o l t a g e w i t h r e s p e c t t o g r o u n d - 0 . 5 4 . 6 v v i d c i n p u t v o l t a g e [ 1 ] w i t h r e s p e c t t o g r o u n d - 2 . 0 5 . 8 v i o u t d c o u t p u t c u r r e n t , p e r p i n - 2 5 2 5 m a t s t g s t o r a g e t e m p e r a t u r e n o b i a s - 6 5 1 5 0 c t a a m b i e n t t e m p e r a t u r e u n d e r b i a s - 6 5 1 3 5 c t j j u n c t i o n t e m p e r a t u r e f i n e l i n e b g a , p q f p , a n d t p f p p a c k a g e s , u n d e r b i a s 1 3 5 c 7 k a t b l 0 3 s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t v c c i n t s u p p l y v o l t a g e , i n t e r n a l l o g i c a n d i n p u t b u f f e r s 3 . 0 3 . 6 v v c c i o s u p p l y v o l t a g e f o r o u t p u t d r i v e r s 3 . 3 v o l t o p e r a t i o n 3 . 0 3 . 6 v 2 . 5 v o l t o p e r a t i o n 2 . 3 2 . 7 v v i i n p u t v o l t a g e - 0 . 5 5 . 7 5 v v o o u t p u t v o l t a g e 0 v c c i o v a m b i e n t o p e r a t i n g t e m p e r a t u r e c o m m e r c i a l t e m p e r a t u r e r a n g e 0 7 0 c i n d u s t r i a l t e m p e r a t u r e r a n g e - 4 0 8 5 c a m b i e n t o p e r a t i n g t e m p e r a t u r e c o m m e r c i a l t e m p e r a t u r e r a n g e 0 9 0 c i n d u s t r i a l t e m p e r a t u r e r a n g e - 4 0 1 0 5 c t r i n p u t s i g n a l r i s e t i m e 4 0 n s t f i n p u t s i g n a l f a l l t i m e 4 0 n s t r v c c v c c r i s e t i m e 1 0 0 m s t a 7 k a t b l 0 2 t j recommended operating conditions
cl7128a and cl7128ae laser processed logic devices page 7 capacitance dc electrical s pecifications cont. s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t c i n i n p u t c a p a c i t a n c e v i n = 0 v , f = 1 . 0 m h z 8 p f c o u t o u t p u t c a p a c i t a n c e v o u t = 0 v , f = 1 . 0 m h z 8 p f 7 k a t b l 0 5 dc electrical characteristics (over the operating range) s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t v i h h i g h - l e v e l i n p u t v o l t a g e 1 . 7 5 . 7 5 v v i l i n p u t l o w v o l t a g e [ 1 ] - 0 . 5 0 . 8 v 3 . 3 - v h i g h - l e v e l t t l o u t p u t v o l t a g e i o h = - 8 m a d c , v c c i o = 3 . 0 0 v 2 . 4 v 3 . 3 - v h i g h - l e v e l c m o s o u t p u t v o l t a g e i o h = - 0 . 1 m a d c , v c c i o = 3 . 0 0 v v c c i o - 0 . 2 v i o h = - 1 0 0 m a d c , v c c i o = 2 . 3 0 v 2 . 1 v i o h = - 1 m a d c , v c c i o = 2 . 3 0 v 2 . 0 i o h = - 2 m a d c , v c c i o = 2 . 3 0 v 1 . 7 3 . 3 - v h i g h - l e v e l t t l o u t p u t v o l t a g e i o h = 8 m a d c , v c c i o = 3 . 0 0 v 0 . 4 5 v 3 . 3 - v h i g h - l e v e l c m o s o u t p u t v o l t a g e i o h = 0 . 1 m a d c , v c c i o = 3 . 0 0 v 0 . 2 v i o h = 1 0 0 m a d c , v c c i o = 2 . 3 0 v 0 . 2 v i o h = 1 m a d c , v c c i o = 2 . 3 0 v 0 . 4 v i o h = 2 m a d c , v c c i o = 2 . 3 0 v 0 . 7 v i i n i n p u t l e a k a g e c u r r e n t v i = v c c o r g n d - 1 0 1 0 a i o z o u t p u t l e a k a g e c u r r e n t v o = v c c o r g n d - 1 0 1 0 a 7 k a t b l 0 4 v o h 2 . 5 - v h i g h - l e v e l o u t p u t v o l t a g e v o l 2 . 5 - v h i g h - l e v e l o u t p u t v o l t a g e
cl7128a and cl7128ae laser processed logic devices page 8 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t p d 1 i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 4 . 5 5 . 0 6 . 0 n s t p d 2 i / o i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 4 . 5 5 . 0 6 . 0 n s t s u g l o b a l c l o c k s e t u p t i m e 3 . 0 3 . 2 3 . 7 n s t h g l o b a l c l o c k h o l d t i m e 0 . 0 0 . 0 0 . 0 n s t f s u g l o b a l c l o c k s e t u p t i m e o f f a s t i n p u t 2 . 5 2 . 5 2 . 5 n s t f h g l o b a l c l o c k h o l d t i m e o f f a s t i n p u t 0 . 0 0 . 0 0 . 5 n s t c o 1 g l o b a l c l o c k t o o u t p u t d e l a y c l = 3 5 p f 1 . 0 2 . 8 1 . 0 3 . 0 1 . 0 3 . 3 n s t c h g l o b a l c l o c k h i g h t i m e 2 . 0 2 . 0 3 . 0 n s t c l g l o b a l c l o c k l o w t i m e 2 . 0 2 . 0 3 . 0 n s t a s u a r r a y c l o c k s e t u p t i m e 1 . 4 1 . 0 0 . 8 n s t a h a r r a y c l o c k h o l d t i m e 0 . 8 0 . 8 1 . 9 n s t a c o 1 a r r a y c l o c k t o o u t p u t d e l a y c l = 3 5 p f 4 . 4 5 . 2 1 . 0 6 . 2 n s t a c h a r r a y c l o c k h i g h t i m e 2 . 0 2 . 0 3 . 0 n s t a c l a r r a y c l o c k l o w t i m e 2 . 0 2 . 0 3 . 0 n s t c n t m i n i m u m g l o b a l c l o c k p e r i o d 5 . 2 5 . 5 6 . 4 n s f c n t m a x . i n t e r n a l g l o b a l c l o c k f r e q u e n c y 1 9 2 . 3 1 8 1 . 8 1 5 6 . 3 m h z t a c n t m i n i m u m a r r a y c l o c k p e r i o d 5 . 2 5 . 5 6 . 4 n s f a c n t m a x . i n t e r n a l a r r a y c l o c k f r e q u e n c y 1 9 2 . 3 1 8 1 . 8 1 5 6 . 3 m h z s y m b o l 7 k a t b l 0 6 a 1 s p e e d : - 4 s p e e d : - 5 s p e e d : - 6 ac electrical s pecifications i/o element timing parameters
cl7128a and cl7128ae laser processed logic devices page 9 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t p d 1 i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 7 . 5 1 0 . 0 1 2 . 0 n s t p d 2 i / o i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 7 . 5 1 0 . 0 1 2 . 0 n s t s u g l o b a l c l o c k s e t u p t i m e 4 . 9 6 . 6 7 . 8 n s t h g l o b a l c l o c k h o l d t i m e 0 . 0 0 . 0 0 . 0 n s t f s u g l o b a l c l o c k s e t u p t i m e o f f a s t i n p u t 3 . 0 3 . 0 3 . 0 n s t f h g l o b a l c l o c k h o l d t i m e o f f a s t i n p u t 0 . 0 0 . 0 0 . 0 n s t c o 1 g l o b a l c l o c k t o o u t p u t d e l a y c l = 3 5 p f 1 . 0 4 . 5 1 . 0 5 . 9 1 . 0 7 . 1 n s t c h g l o b a l c l o c k h i g h t i m e 3 . 0 4 . 0 5 . 0 n s t c l g l o b a l c l o c k l o w t i m e 3 . 0 4 . 0 5 . 0 n s t a s u a r r a y c l o c k s e t u p t i m e 1 . 6 2 . 1 2 . 4 n s t a h a r r a y c l o c k h o l d t i m e 2 . 1 3 . 4 4 . 4 n s t a c o 1 a r r a y c l o c k t o o u t p u t d e l a y c l = 3 5 p f 7 . 8 1 0 . 4 1 2 . 5 n s t a c h a r r a y c l o c k h i g h t i m e 3 . 0 4 . 0 5 . 0 n s t a c l a r r a y c l o c k l o w t i m e 3 . 0 4 . 0 5 . 0 n s t c n t m i n i m u m g l o b a l c l o c k p e r i o d 8 . 4 1 1 . 2 1 3 . 3 n s f c n t m a x . i n t e r n a l g l o b a l c l o c k f r e q u e n c y 1 1 9 . 0 8 9 . 3 7 5 . 2 m h z t a c n t m i n i m u m a r r a y c l o c k p e r i o d 8 . 4 1 1 . 2 1 3 . 3 n s f a c n t m a x . i n t e r n a l a r r a y c l o c k f r e q u e n c y 1 1 9 . 0 8 9 . 3 7 5 . 2 m h z s y m b o l 7 k a t b l 0 6 a 2 s p e e d : - 7 s p e e d : - 1 0 s p e e d : - 1 2 external timing parameters ac electrical s pecifications cont.
cl7128a and cl7128ae laser processed logic devices page 10 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t i n i n p u t p a d a n d b u f f e r d e l a y 0 . 3 0 . 3 0 . 3 n s t i o i / o i n p u t p a d a n d b u f f e r d e l a y 0 . 3 0 . 3 0 . 3 n s t f i n f a s t i n p u t d e l a y 2 . 6 2 . 6 2 . 4 n s t s e x p s h a r e d e x p a n d e r d e l a y 1 . 9 2 . 4 2 . 8 n s t p e x p p a r a l l e l e x p a n d e r d e l a y 0 . 6 0 . 6 0 . 5 n s t l a d l o g i c a r r a y d e l a y 1 . 9 2 . 5 2 . 5 n s t l a c l o g i c c o n t r o l a r r a y d e l a y 1 . 8 2 . 3 2 . 5 n s t i o e i n t e r n a l o u t p u t e n a b l e d e l a y 0 . 0 0 . 0 0 . 2 n s o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v t x z o u t p u t b u f f e r d i s a b l e d e l a y c l = 5 p f [ 3 ] 4 . 0 4 . 0 4 . 0 n s t s u r e g i s t e r s e t u p t i m e 1 . 4 0 . 8 1 . 0 n s t h r e g i s t e r h o l d t i m e 0 . 8 1 . 0 1 . 7 n s t f s u r e g i s t e r s e t u p t i m e o f f a s t i n p u t 0 . 9 0 . 8 1 . 2 n s t f h r e g i s t e r h o l d t i m e o f f a s t i n p u t 1 . 6 1 . 7 1 . 3 n s t r d r e g i s t e r d e l a y 1 . 2 1 . 4 1 . 6 n s t c o m b c o m b i n a t o r i a l d e l a y 1 . 3 1 . 0 1 . 6 n s t i c a r r a y c l o c k d e l a y 1 . 9 2 . 3 2 . 7 n s t e n r e g i s t e r e n a b l e t i m e 1 . 8 2 . 3 2 . 5 n s t g l o b g l o b a l c o n t r o l d e l a y 1 . 0 0 . 9 1 . 1 n s t p r e r e g i s t e r p r e s e t t i m e 2 . 3 2 . 6 2 . 3 n s t c l r r e g i s t e r c l e a r t i m e 2 . 3 2 . 6 2 . 3 n s t l i a l i a d e l a y 0 . 7 0 . 8 1 . 3 n s s p e e d : - 4 s p e e d : - 5 s p e e d : - 6 s y m b o l t o d 1 c l = 3 5 p f 0 . 3 0 . 4 0 . 3 n s t o d 2 c l = 3 5 p f 0 . 8 0 . 9 0 . 8 n s t o d 3 c l = 3 5 p f 5 . 3 5 . 4 5 . 3 n s t z x 1 c l = 3 5 p f 4 . 0 4 . 0 4 . 0 n s t z x 2 c l = 3 5 p f 4 . 5 4 . 5 9 . 0 9 . 0 t z x 3 c l = 3 5 p f 9 . 0 n s 7 k a t b l 0 7 a 1 4 . 5 n s ac electrical s pecifications cont. internal timing parameters [4]
cl7128a and cl7128ae laser processed logic devices page 11 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t i n i n p u t p a d a n d b u f f e r d e l a y 0 . 4 0 . 6 0 . 7 n s t i o i / o i n p u t p a d a n d b u f f e r d e l a y 0 . 4 0 . 6 0 . 7 n s t f i n f a s t i n p u t d e l a y 3 . 3 3 . 7 4 . 1 n s t s e x p s h a r e d e x p a n d e r d e l a y 3 . 6 4 . 9 5 . 9 n s t p e x p p a r a l l e l e x p a n d e r d e l a y 0 . 8 1 . 1 1 . 3 n s t l a d l o g i c a r r a y d e l a y 3 . 7 5 . 0 6 . 0 n s t l a c l o g i c c o n t r o l a r r a y d e l a y 3 . 4 4 . 6 5 . 6 n s t i o e i n t e r n a l o u t p u t e n a b l e d e l a y 0 . 0 0 . 0 0 . 0 n s o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v t x z o u t p u t b u f f e r d i s a b l e d e l a y c l = 5 p f [ 3 ] 4 . 0 5 . 0 5 . 0 n s t s u r e g i s t e r s e t u p t i m e 1 . 3 1 . 7 2 . 0 n s t h r e g i s t e r h o l d t i m e 2 . 4 3 . 8 4 . 8 n s t f s u r e g i s t e r s e t u p t i m e o f f a s t i n p u t 1 . 1 1 . 1 1 . 1 n s t f h r e g i s t e r h o l d t i m e o f f a s t i n p u t 1 . 9 1 . 9 1 . 9 n s t r d r e g i s t e r d e l a y 2 . 1 2 . 8 3 . 3 n s t c o m b c o m b i n a t o r i a l d e l a y 1 . 5 2 . 0 2 . 4 n s t i c a r r a y c l o c k d e l a y 3 . 4 4 . 6 5 . 6 n s t e n r e g i s t e r e n a b l e t i m e 3 . 4 4 . 6 5 . 6 n s t g l o b g l o b a l c o n t r o l d e l a y 1 . 4 1 . 8 2 . 2 n s t p r e r e g i s t e r p r e s e t t i m e 3 . 9 5 . 2 6 . 2 n s t c l r r e g i s t e r c l e a r t i m e 3 . 9 5 . 2 6 . 2 n s t l i a l i a d e l a y 1 . 3 1 . 7 2 . 0 n s s p e e d : - 7 s p e e d : - 1 0 s p e e d : - 1 2 s y m b o l t o d 1 c l = 3 5 p f 0 . 6 0 . 7 0 . 9 n s t o d 2 c l = 3 5 p f 1 . 1 1 . 2 0 . 4 n s t o d 3 c l = 3 5 p f 5 . 6 5 . 7 5 . 9 n s t z x 1 c l = 3 5 p f 4 . 0 5 . 0 5 . 0 n s t z x 2 c l = 3 5 p f 4 . 5 5 . 5 9 . 0 1 0 . 0 t z x 3 c l = 3 5 p f 1 0 . 0 n s 7 k a t b l 0 7 a 2 5 . 5 n s ac electrical s pecifications cont. internal timing parameters [4]
cl7128a and cl7128ae laser processed logic devices page 12 1. during transitions, inputs may undershoot to -2.0v for periods shorter than 20ns. otherwise, minimum dc input voltage is 0.3v. 2. typical values are at v cc of 5.0 volts and ambient temperature of 25 oc. 3. guaranteed but not tested. characterized initially, and after any design changes which may affect these parameters. 4. internal timing delays are based on characterization, and cannot be explicitly tested. internal timing parameters should be used for performance estimation only. 11 jan. 1999: created preliminary document. 31 july 1999: created full document. 13 oct. 1999: corrected typographical error in ac test condition diagram (w changed to w ) also corrected timing in 10ns external timing paramiters 1 dec. 2000: updated application note reference. ac t est conditions 464 w 250 w 35 pf v ccio output includes jig capacitance 464 w 250 w 5 pf v ccio output includes jig capacitance (a) (b) 3ns 3ns 3.0v 90% 10% gnd 90% 10% all input pulses 7 k d r w 0 2 a notes to t ables revision history
cl7128a and cl7128ae laser processed logic devices page 13 p a r t n u m b e r t e m p e r a t u r e r a n g e p a c k a g e t y p e s p e e d a l t e r a e q u i v a l e n t c l 7 1 2 8 a l c 8 4 - 1 2 c o m m e r c i a l 8 4 - p i n p l a s t i c l c c - 1 2 e p m 7 1 2 8 a l c 8 4 - 1 2 c l 7 1 2 8 a l c 8 4 - 1 0 - 1 0 e p m 7 1 2 8 a l c 8 4 - 1 0 c l 7 1 2 8 a l c 8 4 - 7 - 7 e p m 7 1 2 8 a l c 8 4 - 7 c l 7 1 2 8 a l c 8 4 - 6 - 6 e p m 7 1 2 8 a l c 8 4 - 6 c l 7 1 2 8 a l c 8 4 - 5 - 5 e p m 7 1 2 8 a l c 8 4 - 5 c l 7 1 2 8 a l c 8 4 - 4 - 4 n / a c l 7 1 2 8 a t c 1 0 0 - 1 2 1 0 0 - p i n t h i n q f p - 1 2 e p m 7 1 2 8 a t c 1 0 0 - 1 2 c l 7 1 2 8 a t c 1 0 0 - 1 0 - 1 0 e p m l 7 1 2 8 a t c 1 0 0 - 1 0 c l 7 1 2 8 a t c 1 0 0 - 7 - 7 e p m 7 1 2 8 a t c 1 0 0 - 7 c l 7 1 2 8 a t c 1 0 0 - 6 - 6 e p m 7 1 2 8 a t c 1 0 0 - 6 c l 7 1 2 8 a t c 1 0 0 - 5 - 5 e p m 7 1 2 8 a t c 1 0 0 - 5 c l 7 1 2 8 a t c 1 0 0 - 4 - 4 n / a c l 7 1 2 8 a t i 1 0 0 - 1 0 i n d u s t r i a l - 1 0 e p m l 7 1 2 8 a t i 1 0 0 - 1 0 c l 7 1 2 8 a f c 1 0 0 - 1 2 c o m m e r c i a l 1 0 0 - p i n f b g a - 1 2 e p m 7 1 2 8 a f c 1 0 0 - 1 2 c l 7 1 2 8 a f c 1 0 0 - 1 0 - 1 0 e p m 7 1 2 8 a f c 1 0 0 - 1 0 c l 7 1 2 8 a f c 1 0 0 - 7 - 7 e p m 7 1 2 8 a f c 1 0 0 - 7 c l 7 1 2 8 a f c 1 0 0 - 6 - 6 e p m 7 1 2 8 a f c 1 0 0 - 6 c l 7 1 2 8 a f c 1 0 0 - 5 - 5 e p m 7 1 2 8 a f c 1 0 0 - 5 c l 7 1 2 8 a f c 1 0 0 - 4 - 4 n / a c l 7 1 2 8 a t c 1 4 4 - 1 2 1 4 4 - p i n t h i n q f p - 1 2 e p m 7 1 2 8 a t c 1 4 4 - 1 2 c l 7 1 2 8 a t c 1 4 4 - 1 0 - 1 0 e p m 7 1 2 8 a t c 1 4 4 - 1 0 c l 7 1 2 8 a t c 1 4 4 - 7 - 7 e p m 7 1 2 8 a t c 1 4 4 - 7 c l 7 1 2 8 a t c 1 4 4 - 6 - 6 e p m 7 1 2 8 a t c 1 4 4 - 6 c l 7 1 2 8 a t c 1 4 4 - 5 - 5 e p m 7 1 2 8 a t c 1 4 4 - 5 c l 7 1 2 8 a t c 1 4 4 - 4 - 4 n / a c l 7 1 2 8 a t i 1 4 4 - 1 0 i n d u s t r i a l - 1 0 e p m 7 1 2 8 a t i 1 4 4 - 1 0 c l 7 1 2 8 a t c 1 4 4 - 1 2 c o m m e r c i a l 2 5 6 - p i n f b g a - 1 2 e p m 7 1 2 8 a t c 1 4 4 - 1 2 c l 7 1 2 8 a t c 1 4 4 - 1 0 - 1 0 e p m 7 1 2 8 a t c 1 4 4 - 1 0 c l 7 1 2 8 a t c 1 4 4 - 7 - 7 e p m 7 1 2 8 a t c 1 4 4 - 7 c l 7 1 2 8 a t c 1 4 4 - 6 - 6 e p m 7 1 2 8 a t c 1 4 4 - 6 c l 7 1 2 8 a t c 1 4 4 - 5 - 5 e p m 7 1 2 8 a t c 1 4 4 - 5 c l 7 1 2 8 a t c 1 4 4 - 4 - 4 n / a 7 1 2 8 a t b l 0 2 ordering information
cl7128a and cl7128ae laser processed logic devices page 14 ordering information (cont.) p a r t n u m b e r t e m p e r a t u r e r a n g e p a c k a g e t y p e s p e e d a l t e r a e q u i v a l e n t c l 7 1 2 8 a e l c 8 4 - 1 0 c o m m e r c i a l 8 4 - p i n p l a s t i c l c c - 1 0 e p m 7 1 2 8 a e l c 8 4 - 1 0 c l 7 1 2 8 a e l c 8 4 - 7 - 7 e p m 7 1 2 8 a e l c 8 4 - 7 c l 7 1 2 8 a e l c 8 4 - 6 - 6 e p m 7 1 2 8 a e l c 8 4 - 6 c l 7 1 2 8 a e l c 8 4 - 5 - 5 e p m 7 1 2 8 a e l c 8 4 - 5 c l 7 1 2 8 a e l c 8 4 - 4 - 4 n / a c l 7 1 2 8 a e t c 1 0 0 - 1 0 1 0 0 - p i n t h i n q f p - 1 0 e p m l 7 1 2 8 a e t c 1 0 0 - 1 0 c l 7 1 2 8 a e t c 1 0 0 - 7 - 7 e p m 7 1 2 8 a e t c 1 0 0 - 7 c l 7 1 2 8 a e t c 1 0 0 - 6 - 6 e p m 7 1 2 8 a e t c 1 0 0 - 6 c l 7 1 2 8 a e t c 1 0 0 - 5 - 5 e p m 7 1 2 8 a e t c 1 0 0 - 5 c l 7 1 2 8 a e t c 1 0 0 - 4 - 4 n / a c l 7 1 2 8 a e t i 1 0 0 - 7 i n d u s t r i a l - 7 e p m l 7 1 2 8 a e t i 1 0 0 - 7 c l 7 1 2 8 a e f c 1 0 0 - 1 0 c o m m e r c i a l 1 0 0 - p i n f b g a - 1 0 e p m 7 1 2 8 a e f c 1 0 0 - 1 0 c l 7 1 2 8 a e f c 1 0 0 - 7 - 7 e p m 7 1 2 8 a e f c 1 0 0 - 7 c l 7 1 2 8 a e f c 1 0 0 - 6 - 6 e p m 7 1 2 8 a e f c 1 0 0 - 6 c l 7 1 2 8 a e f c 1 0 0 - 5 - 5 e p m 7 1 2 8 a e f c 1 0 0 - 5 c l 7 1 2 8 a e f c 1 0 0 - 4 - 4 n / a c l 7 1 2 8 a e f i 1 0 0 - 7 i n d u s t r i a l - 7 e p m 7 1 2 8 a e f i 1 0 0 - 7 c l 7 1 2 8 a e t c 1 4 4 - 1 0 c o m m e r c i a l 1 4 4 - p i n t h i n q f p - 1 0 e p m 7 1 2 8 a e t c 1 4 4 - 1 0 c l 7 1 2 8 a e t c 1 4 4 - 7 - 7 e p m 7 1 2 8 a e t c 1 4 4 - 7 c l 7 1 2 8 a e t c 1 4 4 - 6 - 6 e p m 7 1 2 8 a e t c 1 4 4 - 6 c l 7 1 2 8 a e t c 1 4 4 - 5 - 5 e p m 7 1 2 8 a e t c 1 4 4 - 5 c l 7 1 2 8 a e t c 1 4 4 - 4 - 4 n / a c l 7 1 2 8 a e t i 1 4 4 - 7 i n d u s t r i a l - 7 e p m 7 1 2 8 a e t i 1 4 4 - 7 c l 7 1 2 8 a e t c 1 4 4 - 1 0 c o m m e r c i a l 2 5 6 - p i n f b g a - 1 0 e p m 7 1 2 8 a e t c 1 4 4 - 1 0 c l 7 1 2 8 a e t c 1 4 4 - 7 - 7 e p m 7 1 2 8 a e t c 1 4 4 - 7 c l 7 1 2 8 a e t c 1 4 4 - 6 - 6 e p m 7 1 2 8 a e t c 1 4 4 - 6 c l 7 1 2 8 a e t c 1 4 4 - 5 - 5 e p m 7 1 2 8 a e t c 1 4 4 - 5 c l 7 1 2 8 a e t c 1 4 4 - 4 - 4 n / a 7 1 2 8 a t b l 0 3

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